Testing has emerged as a key constraint in the push for more advanced, reliable and cost-effective semiconductor based products. Advances in semiconductor process technology have enabled chip designers to pack high volume production chips with 100 million transistors. Experts predict this will increase to more than 1 billion transistors within the next few years.
Semiconductor process technology is characterized by Moore's Law, which states that the numbers of transistors in a given surface area will double every 18 months. Much of this density increase is driven by smaller and smaller line widths or geometries. Today 90 nm devices are common and 25 nm designs are in development (a nanometer is one millionth of a meter or 1/1200th width of human hair). These advances place a strain on test systems as more transistors and structures must be tested. This exponential growth rate also drives a continual increase in the process, design and manufacturing complexities which, in turn, can increase systemic problems that affect quality, yield and product reliability. All of these factors tend to drive the need for more test time and more comprehensive testing, thus test cost has become a major factor in the overall manufacturing cost of an integrated circuit.
It will now be illuminated some terms used in semiconductor testing industry:                An integrated circuit (IC) is a small electronic device made out of a semiconductor material.        A wafer is a thin slice of semiconductor material, such as silicon, upon which microcircuits are constructed by doping (for example, diffusion or ion implantation), etching, and deposition of various materials.        A wafer is usually made up of many single units also called dice (one unit=die, two or more units=dice). After the fabrication process is completed, the wafer will be cut during the assembly process and each die may be connected into a package using aluminum (or occasionally gold) wires which are welded to pads, usually found around the edge of the die.        There are various testing stages. For example, sort (also known as wafer probe) is done while the units are still at wafer level. For example, final test is done after the units have been packaged.        A “touchdown” is the term used when the interface unit (either at Sort—probe-card or Final Test—contactor) “touches” the unit under test. In parallel testing, units tested at the same time have the same touchdown.        Note that the term device may have many meanings in semiconductor testing, including integrated circuits, product type, wafer or die and the meaning can be construed based on the context.        The term lot may also have more than one meaning in semiconductor testing. Typically although not necessarily in fabrication and sort test, a lot refers to a plurality of wafers that were manufactured at the same time, whereas in assembly/final test, a lot typically although not necessarily refers to a plurality of units that were tested in the same batch.        
In one test floor configuration, there are one or more testing stations. In each station there are a tester (test equipment) and a prober or handler (the prober is configured to handle a wafer and the handler is configured to handle an individual unit). The tester and prober/handler together are considered the test module. On the prober/handler sits an interface unit—probe-card or contactor configured to hold a wafer or individual packaged unit. One or more station controllers control the tester and the prober/handler. For example one station controller may control both the tester and the prober/handler. As another example one station controller may control the tester and another station controller may control the prober/handler. Upon receiving instructions from the controlling station controller, the prober/handler takes the device to the tester so that the tester can test device. Typically although not necessarily, the tester and the station controller include programs which when run cause the tester and the station controller to perform the testing in accordance with the programs.
Currently testing is performed by two basic methods. Either, devices are tested a single one at a time, sequentially, or several are tested at the same time in “parallel”. Single tests are more common with complex products such as CPUs while memory devices are most often tested in parallel. Note, however, that these examples are not binding. Currently, there are various test sockets (aka operations or stages) for a given product that together comprise a test flow. A test socket is an operation that may be distinguished by a specific testing type at specific test conditions. For instance, for a given socket, a set of tests is performed at a given temperature, whereas for another socket, the same (or similar) tests are performed at a different temperature. By way of another example, functional tests are applied at the first socket and structural tests are applied at the second socket. Test sockets include (again, non-binding): E-test (or parametric electrical testing), Sort (or wafer probe test), Burn-in, Final Test, and System Validation. Each socket may include various sub-steps such as Sort1, Sort2 and Sort3. Sort is done while the dice (aka devices or units) are still at the wafer level whereas at Final test, the semiconductor devices have been packaged. The main goal of the specified stages is to separate out potentially good devices from those that fail testing. Electrical parametric tests are executed on the wafers scribe line (between the dice) and usually measure transistor parametric characteristics. Burn-in is executed, after packaging, in order to simulate an extended life cycle by stressing the devices at a high temperature (in a burn-in oven) while applying an elevated voltage at an extended duration. It is important to note that there are various types of burn-in. Some methods only “bake” the devices at a high temperature, others apply an elevated voltage as well and some perform all this while executing a functional pattern (with high toggle coverage) on the device IO's. System validation is performed usually as the last step by testing the device in “customer mode”. For example a CPU device will be placed on an actual motherboard and “booted-up” using an operating system as well as testing other software applications. In summary, every product may go through a different flow. In addition, not all devices of the same product may go through the entire flow. For example, burn-in and system validation are good examples where devices are tested in “sample mode”.